501 search results - page 26 / 101 » Evaluating CMPs and Their Memory Architecture |
172
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WSC
1997
15 years 7 months ago
1997
We present a system for describing and solving closed queuing network models of the memory access performance of NUMA architectures. The system consists of a model description lan...
162
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SASP
2009
IEEE
16 years 18 days ago
2009
IEEE
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
190
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ISCA
2009
IEEE
16 years 15 days ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
272
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MICRO
2000
IEEE
15 years 5 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
133
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VLSID
2006
IEEE
15 years 12 months ago
2006
IEEE
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...