501 search results - page 46 / 101 » Evaluating CMPs and Their Memory Architecture |
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
DAC
1999
ACM
14 years 23 hour ago
1999
ACM
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC . The novel feature of the approach is the use an embedde...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...