501 search results - page 75 / 101 » Evaluating CMPs and Their Memory Architecture |
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
SBACPAD
2003
IEEE
14 years 28 days ago
2003
IEEE
— A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling informatio...
SAC
2009
ACM
14 years 9 days ago
2009
ACM
The future of service-centric environments suggests that organizations will dynamically discover and utilize web services for new business processes particularly those that span m...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...