201 search results - page 13 / 41 » Evaluating Run-Time Techniques for Leakage Power Reduction |
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...