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» Evaluating Run-Time Techniques for Leakage Power Reduction
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TVLSI
2002
121views more  TVLSI 2002»
13 years 7 months ago
On-chip decoupling capacitor optimization using architectural level prediction
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills
ISVLSI
2008
IEEE
142views VLSI» more  ISVLSI 2008»
14 years 2 months ago
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
Venkataraman Mahalingam, Nagarajan Ranganathan
CCGRID
2007
IEEE
14 years 1 months ago
Integrated Data Reorganization and Disk Mapping for Reducing Disk Energy Consumption
Increasing power consumption of high-performance systems leads to reliability, survivability, and cooling related problems. Motivated by this observation, several recent efforts f...
Seung Woo Son, Mahmut T. Kandemir
ESOP
2006
Springer
13 years 11 months ago
Pure Pattern Calculus
Abstract. The pure pattern calculus generalises the pure lambda-calculus by basing computation on pattern-matching instead of beta-reduction. The simplicity and power of the calcul...
C. Barry Jay, Delia Kesner
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier