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3DIC
2009
IEEE
120views Hardware» more  3DIC 2009»
14 years 2 months ago
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuw...
LCN
2003
IEEE
14 years 22 days ago
A User-level Multicast Performance Comparison of Scalable Coherent Interface and Myrinet Interconnects
This paper compares and evaluates the multicast performance of two of the most widely deployed System-Area Networks (SANs), Dolphin’s Scalable Coherent Interface (SCI) and Myric...
Sarp Oral, Alan D. George
PE
2008
Springer
143views Optimization» more  PE 2008»
13 years 7 months ago
Improving the performance of large interconnection networks using congestion-control mechanisms
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
José Miguel-Alonso, Cruz Izu, José-&...
ICCAD
2008
IEEE
80views Hardware» more  ICCAD 2008»
14 years 4 months ago
Advancing supercomputer performance through interconnection topology synthesis
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
Yi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan...
NOCS
2007
IEEE
14 years 1 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston