Sciweavers

392 search results - page 77 / 79
» Evaluation of streaming aggregation on parallel hardware arc...
Sort
View
ICS
1999
Tsinghua U.
13 years 11 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...
HPCA
2007
IEEE
14 years 7 months ago
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging
Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Unfortuna...
Guru Venkataramani, Brandyn Roemer, Yan Solihin, M...
HPCA
2005
IEEE
14 years 7 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
ISCA
2008
IEEE
139views Hardware» more  ISCA 2008»
14 years 1 months ago
Atom-Aid: Detecting and Surviving Atomicity Violations
Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They h...
Brandon Lucia, Joseph Devietti, Karin Strauss, Lui...
IEEEPACT
2006
IEEE
14 years 1 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal