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ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 10 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 4 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
CODES
2007
IEEE
14 years 2 months ago
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology ...
Mark Thompson, Hristo Nikolov, Todor Stefanov, And...
NETGAMES
2006
ACM
14 years 2 months ago
A new approach on wearable game design and its evaluation
As technologies evolve and computer systems shrink to the size of matchboxes, also their field of application shifts in new directions. Our permanent companions, mobile phones, p...
Christian Bertelsmeyer, Erik Koch, Alexander H. Sc...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
14 years 1 months ago
Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing
The nature of IC design has is necessarily evolving to a more data-centric design flow in which EDA tools share a common information in a design database without the negative cost...
D. R. Cottrell, T. J. Grebinski