—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
Abstract. Software configurable analogue arrays offer an intriguing platform for automated design by evolutionary algorithms. Like previous evolvable hardware experiments, these pl...
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
In this paper, we propose a diagnostic test generation method in conjunction with an efficient sequential SAT-based diagnosis procedure to precisely identify multiple defective si...