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TCAD
1998
119views more  TCAD 1998»
13 years 6 months ago
A controller redesign technique to enhance testability of controller-data path circuits
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
ISCAS
2007
IEEE
169views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang
EVOW
2008
Springer
13 years 8 months ago
Analogue Circuit Control through Gene Expression
Abstract. Software configurable analogue arrays offer an intriguing platform for automated design by evolutionary algorithms. Like previous evolvable hardware experiments, these pl...
Kester Clegg, Susan Stepney
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
ICCD
2005
IEEE
124views Hardware» more  ICCD 2005»
14 years 3 months ago
Accurate Diagnosis of Multiple Faults
In this paper, we propose a diagnostic test generation method in conjunction with an efficient sequential SAT-based diagnosis procedure to precisely identify multiple defective si...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng