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» Exact combinational logic synthesis and non-standard circuit...
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DAC
2003
ACM
14 years 10 months ago
Making cyclic circuits acyclic
Cyclic circuits that do not hold state or oscillate are often the most convenient representation for certain functions, such as arbiters, and can easily be produced inadvertently ...
Stephen A. Edwards
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
14 years 3 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
CAV
2010
Springer
286views Hardware» more  CAV 2010»
13 years 9 months ago
ABC: An Academic Industrial-Strength Verification Tool
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
Robert K. Brayton, Alan Mishchenko
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
DAC
2008
ACM
14 years 10 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes