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ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
13 years 11 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
ISIPTA
2003
IEEE
111views Mathematics» more  ISIPTA 2003»
14 years 27 days ago
The DecideIT Decision Tool
The nature of much information available to decision makers is vague and imprecise, be it information for human managers in organisations or for process agents in a distributed co...
Mats Danielson, Love Ekenberg, Jim Johansson, Aron...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 27 days ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
MDM
2009
Springer
201views Communications» more  MDM 2009»
14 years 2 months ago
OntoMobiLe: A Generic Ontology-Centric Service-Oriented Architecture for Mobile Learning
Creation of pedagogical learning models to handle the specificity of mobile learning and the inherent constraints of mobile devices is a fundamental challenge in mobile learning. ...
Keng Y. Yee, Wee Tiong Ang, Flora S. Tsai, Rajaram...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 1 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...