453 search results - page 14 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
ICPADS
2002
IEEE
14 years 16 days ago
2002
IEEE
This paper presents the study and results of running several core multimedia applications on a simultaneous multithreading (SMT) architecture, including some detailed analysis ran...
MICRO
2008
IEEE
13 years 7 months ago
2008
IEEE
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
ISCA
2010
IEEE
14 years 21 days ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...