453 search results - page 81 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
Device scaling and large scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing par...
EDCC
2006
Springer
13 years 11 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Bridging the gap between model-based design and platformbased implementation is one of the critical challenges for embedded software systems. In the context of embedded control sy...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
FPL
2003
Springer
14 years 25 days ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...