Sciweavers

774 search results - page 26 / 155
» Experiences of low power design implementation and verificat...
Sort
View
CHES
2004
Springer
121views Cryptology» more  CHES 2004»
14 years 2 months ago
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?
Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to di...
François-Xavier Standaert, Siddika Berna &O...
SIGCOMM
2010
ACM
13 years 9 months ago
NapSAC: design and implementation of a power-proportional web cluster
Energy consumption is a major and costly problem in data centers. A large fraction of this energy goes to powering idle machines that are not doing any useful work. We identify tw...
Andrew Krioukov, Prashanth Mohan, Sara Alspaugh, L...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
14 years 13 days ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 5 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 9 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal