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DAC
2004
ACM
14 years 9 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
14 years 19 days ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
TVLSI
2010
13 years 3 months ago
Low-Power Multimedia System Design by Aggressive Voltage Scaling
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanle...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 5 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
AES
2004
Springer
190views Cryptology» more  AES 2004»
14 years 2 months ago
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
Elena Trichina, Tymur Korkishko, Kyung-Hee Lee