53 search results - page 5 / 11 » Explaining Dynamic Cache Partitioning Speed Ups |
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
ICPP
2003
IEEE
14 years 1 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
CG
2005
Springer
13 years 7 months ago
2005
Springer
We propose an efficient framework for dynamic cloud rendering. Base on the proposed simplified lighting model, the Shadow Relation Table (SRT) and Metaball Lighting Texture Databa...
ICPP
2003
IEEE
14 years 1 months ago
2003
IEEE
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...