375 search results - page 12 / 75 » Explicit gate delay model for timing evaluation |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...