375 search results - page 7 / 75 » Explicit gate delay model for timing evaluation |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
JCM
2006
13 years 7 months ago
2006
The Internet is undergoing changes of its traffic mix, with the IP-based interactive multimedia applications gaining momentum. According to studies, UDP-based multimedia traffic ha...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
ICCAD
1991
IEEE
13 years 11 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...