87 search results - page 9 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
EDCC
2008
Springer
13 years 9 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
DFT
2000
IEEE
13 years 12 months ago
2000
IEEE
1 Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In particular, safety-critical computer-based applications are hitting ...
CAL
2006
13 years 7 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...