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» Exploiting Value Locality in Physical Register Files
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HPCA
2006
IEEE
14 years 9 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
TVLSI
2002
102views more  TVLSI 2002»
13 years 8 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
14 years 3 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
14 years 1 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
IWDC
2005
Springer
117views Communications» more  IWDC 2005»
14 years 2 months ago
Oasis: A Hierarchical EMST Based P2P Network
Peer-to-peer systems and applications are distributed systems without any centralized control. P2P systems form the basis of several applications, such as file sharing systems and ...
Pankaj Ghanshani, Tarun Bansal