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» Exploiting loop-dependent stream reuse for stream processors
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VLDB
2007
ACM
145views Database» more  VLDB 2007»
14 years 7 months ago
Executing Stream Joins on the Cell Processor
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
Bugra Gedik, Philip S. Yu, Rajesh Bordawekar
ICS
2007
Tsinghua U.
14 years 1 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally
HIPEAC
2009
Springer
14 years 2 months ago
Mapping and Synchronizing Streaming Applications on Cell Processors
Developing streaming applications on heterogenous multi-processor architectures like the Cell is difficult. Currently, application developers need to know about hardware details t...
Maik Nijhuis, Herbert Bos, Henri E. Bal, Cé...
ICDE
2005
IEEE
144views Database» more  ICDE 2005»
14 years 9 months ago
Dynamic Load Distribution in the Borealis Stream Processor
Distributed and parallel computing environments are becoming cheap and commonplace. The availability of large numbers of CPU's makes it possible to process more data at highe...
Ying Xing, Stanley B. Zdonik, Jeong-Hyon Hwang
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...