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IPPS
2008
IEEE
14 years 1 months ago
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
S. Huang, Y. Luo, W. Feng
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
13 years 11 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
JSS
2007
169views more  JSS 2007»
13 years 7 months ago
MDABench: Customized benchmark generation using MDA
This paper describes an approach for generating customized benchmark suites from a software architecture description following a Model Driven Architecture (MDA) approach. The benc...
Liming Zhu, Ngoc Bao Bui, Yan Liu, Ian Gorton
DAC
2005
ACM
13 years 9 months ago
Asynchronous circuits transient faults sensitivity evaluation
1 This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circui...
Yannick Monnet, Marc Renaudin, Régis Leveug...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 4 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik