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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 7 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
GECCO
2007
Springer
163views Optimization» more  GECCO 2007»
14 years 4 months ago
Interactive evolution of XUL user interfaces
We attack the problem of user fatigue by using an interactive genetic algorithm to evolve user interfaces in the XUL interface definition language. The interactive genetic algori...
Juan C. Quiroz, Sushil J. Louis, Sergiu M. Dascalu
EMSOFT
2007
Springer
14 years 4 months ago
Methods for multi-dimensional robustness optimization in complex embedded systems
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
Arne Hamann, Razvan Racu, Rolf Ernst
CASES
2006
ACM
14 years 4 months ago
Scalable subgraph mapping for acyclic computation accelerators
Computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common ...
Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami ...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...