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ICS
2009
Tsinghua U.
14 years 5 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
14 years 5 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
IEEEPACT
2009
IEEE
14 years 5 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
IROS
2009
IEEE
198views Robotics» more  IROS 2009»
14 years 5 months ago
Scalable learning for object detection with GPU hardware
Abstract— We consider the problem of robotic object detection of such objects as mugs, cups, and staplers in indoor environments. While object detection has made significant pro...
Adam Coates, Paul Baumstarck, Quoc V. Le, Andrew Y...
MICRO
2009
IEEE
103views Hardware» more  MICRO 2009»
14 years 5 months ago
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Tor...