Sciweavers

92 search results - page 14 / 19
» FADIC: Architectural Synthesis applied in IC Design
Sort
View
DAC
1999
ACM
14 years 8 months ago
ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers
This paper presents a synthesis tool ICEBERG for embedded in-circuit emulators (ICE's), that are part of the development environment for microcontroller (or microprocessor)-b...
Ing-Jer Huang, Tai-An Lu
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
13 years 12 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
DAC
2003
ACM
14 years 8 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DATE
2007
IEEE
146views Hardware» more  DATE 2007»
14 years 1 months ago
Data-flow transformations using Taylor expansion diagrams
Abstract: An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical,...
Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-P...
CASES
2003
ACM
14 years 26 days ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara