44 search results - page 5 / 9 » FPGA Technology Mapping for Power Minimization |
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
DAC
1998
ACM
13 years 11 months ago
1998
ACM
Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multipleoutput...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
HAPTICS
2005
IEEE
14 years 1 months ago
2005
IEEE
Wearable haptics necessitates using low power, small, inexpensive tactors that are typically used as pager motors in cellular phones. One of their limitations is that it appears t...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...