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» FPGA interconnect design using logical effort
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DAC
2005
ACM
14 years 8 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 24 days ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
AHS
2007
IEEE
263views Hardware» more  AHS 2007»
14 years 1 months ago
Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C
Since their invention in the 1980s, the logic density of FPGAs has increased exponentially with time. This increase of logic density first led to the development of synthesisable ...
Gildas Genest, Richard Chamberlain, Robin J. Bruce
DAC
2006
ACM
14 years 8 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
ICES
2003
Springer
93views Hardware» more  ICES 2003»
14 years 22 days ago
A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMar...