363 search results - page 1 / 73 » FPGA interconnect design using logical effort |
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...