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» FPGA interconnect design using logical effort
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DOLAP
1998
ACM
13 years 11 months ago
Methodological Framework for Data Warehouse Design
Though designing a data warehouse requires techniques completely different from those adopted for operational systems, no significant effort has been made so far to develop a comp...
Matteo Golfarelli, Stefano Rizzi
DAC
2009
ACM
14 years 8 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
DATE
2002
IEEE
144views Hardware» more  DATE 2002»
14 years 16 days ago
Design Automation for Deepsubmicron: Present and Future
Advancing technology drives design technology and thus design automation EDA. How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
Ralph H. J. M. Otten, Raul Camposano, Patrick Groe...
ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
14 years 4 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
FPL
2000
Springer
119views Hardware» more  FPL 2000»
13 years 11 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...