28 search results - page 4 / 6 » Fast Buffered Delay Estimation Considering Process Variation... |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Process variations cause different behavior of timingdependent effects across different chips. In this work, we analyze one example of timing-dependent effects, crosscoupling ...
TVLSI
2010
13 years 2 months ago
2010
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
DAC
1998
ACM
13 years 11 months ago
1998
ACM
Networked embedded systems are expected to support adaptive streaming audio/video applications with soft real-time constraints. These systems can be designed in a cost efficient ...