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ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
14 years 5 days ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
ASPDAC
1998
ACM
91views Hardware» more  ASPDAC 1998»
14 years 2 days ago
Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening
— This article describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gao’s algorithm by resolving its bottleneck r...
Toshiyuki Hama, Hiroaki Etoh
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 3 days ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
DAC
1998
ACM
14 years 8 months ago
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...
Jason Cong, Patrick H. Madden
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
14 years 2 months ago
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of s...
Tilo Meister, Jens Lienig, Gisbert Thomke