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ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
13 years 12 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
FPL
2000
Springer
130views Hardware» more  FPL 2000»
13 years 11 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
14 years 1 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 4 months ago
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding
Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in modern communication and computer systems. Among the decoding algorithms of RS codes, the rece...
Xinmiao Zhang
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 1 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin