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» Fast and Precise Power Prediction for Combinational Circuits
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ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 9 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
APPT
2009
Springer
14 years 2 months ago
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors
Abstract. With more cores integrated into one single chip, the overall power consumption from the multiple concurrent running programs increases dramatically in a CMP processor whi...
Liqiang He, Cha Narisu
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 1 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
BMCBI
2005
117views more  BMCBI 2005»
13 years 7 months ago
An SVM-based system for predicting protein subnuclear localizations
Background: The large gap between the number of protein sequences in databases and the number of functionally characterized proteins calls for the development of a fast computatio...
Zhengdeng Lei, Yang Dai