49 search results - page 4 / 10 » Fast buffer insertion considering process variations |
ASPDAC
2006
ACM
14 years 29 days ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
AUTOMATICA
2008
13 years 7 months ago
2008
This paper studies a general dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multi...
GLVLSI
2009
IEEE
14 years 1 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...