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» FastRoute: a step to integrate global routing into placement
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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 8 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
14 years 1 months ago
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
Christophe Alexandre, Hugo Clément, Jean-Pa...
ICCAD
2006
IEEE
139views Hardware» more  ICCAD 2006»
14 years 4 months ago
Analog placement with symmetry and other placement constraints
In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for ...
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N...
ISPD
2010
ACM
157views Hardware» more  ISPD 2010»
14 years 2 months ago
SafeChoice: a novel clustering algorithm for wirelength-driven placement
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...
Jackey Z. Yan, Chris Chu, Wai-Kei Mak
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 1 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong