372 search results - page 24 / 75 » Fault simulation on reconfigurable hardware |
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ISQED
2007
IEEE
14 years 3 months ago
2007
IEEE
We present a methodology for the simulation of soft errors targeting future nano-technological devices. This approach efficiently scales the failure rate of individual devices ac...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
ATS
2010
IEEE
13 years 4 months ago
2010
IEEE
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...