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» Fault simulation on reconfigurable hardware
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VLSISP
2008
123views more  VLSISP 2008»
13 years 9 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 2 months ago
Framework for Fault Analysis and Test Generation in DRAMs
Abstract: With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory t...
Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. v...
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 2 months ago
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults
—With the advancement of CMOS manufacturing process to nano-scale, future shipped microprocessors will be increasingly vulnerable to intermittent faults. Quantitatively character...
Songjun Pan, Yu Hu, Xiaowei Li
ICES
2003
Springer
111views Hardware» more  ICES 2003»
14 years 2 months ago
Spiking Neural Networks for Reconfigurable POEtic Tissue
Abstract. Vertebrate and most invertebrate organisms interact with their environment through processes of adaptation and learning. Such processes are generally controlled by comple...
Jan Eriksson, Oriol Torres, Andrew Mitchell, Gayle...
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
14 years 2 months ago
TranGen: a SAT-based ATPG for path-oriented transition faults
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
Kai Yang, Kwang-Ting Cheng, Li-C. Wang