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» Fault simulation on reconfigurable hardware
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ERSA
2010
199views Hardware» more  ERSA 2010»
13 years 7 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
12 years 4 months ago
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
TVLSI
1998
123views more  TVLSI 1998»
13 years 8 months ago
On-line fault detection for bus-based field programmable gate arrays
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
N. R. Shnidman, William H. Mangione-Smith, Miodrag...
EDCC
2006
Springer
14 years 25 days ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
ATS
2003
IEEE
126views Hardware» more  ATS 2003»
14 years 2 months ago
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...
Zaid Al-Ars, A. J. van de Goor