372 search results - page 44 / 75 » Fault simulation on reconfigurable hardware |
140
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DATE
2007
IEEE
16 years 1 days ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
168
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DATE
2006
IEEE
15 years 11 months ago
2006
IEEE
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizin...
157
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FPGA
2003
ACM
15 years 11 months ago
2003
ACM
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
153
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DFT
2003
IEEE
15 years 11 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
165
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EH
2005
IEEE
15 years 11 months ago
2005
IEEE
Manufacturing processes are a key source of faults in complex hardware systems. Minimizing this impact of manufacturing uncertainties is one way towards achieving fault tolerant s...