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ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 4 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 1 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
DATE
2010
IEEE
169views Hardware» more  DATE 2010»
14 years 24 days ago
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
Daniele Ludovici, Alessandro Strano, Georgi Nedelt...
SASN
2003
ACM
14 years 28 days ago
SECTOR: secure tracking of node encounters in multi-hop wireless networks
In this paper we present SECTOR, a set of mechanisms for the secure verification of the time of encounters between nodes in multi-hop wireless networks. This information can be u...
Srdjan Capkun, Levente Buttyán, Jean-Pierre...
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 3 days ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann