172 search results - page 3 / 35 » FinFET-based SRAM design |
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
ISQED
2010
IEEE
13 years 6 months ago
2010
IEEE
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
INFOCOM
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
TVLSI
2008
13 years 7 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...