172 search results - page 9 / 35 » FinFET-based SRAM design |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In this paper, for the first time, a theory for evaluating dynamic noise margins of SRAM cells is developed analytically. The results allow predicting the transient error suscepti...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...