23 search results - page 2 / 5 » Finding optimal L1 cache configuration for embedded systems |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
ISCA
2012
IEEE
11 years 9 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
ISLPED
2005
ACM
14 years 29 days ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...