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DATE
2007
IEEE
107views Hardware» more  DATE 2007»
14 years 4 months ago
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
K. Van Renterghem, P. Demuytere, Dieter Verhulst, ...
RSP
2000
IEEE
105views Control Systems» more  RSP 2000»
14 years 2 months ago
Processor Models for Retargetable Tools
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...
Rajat Moona
ASAP
2003
IEEE
141views Hardware» more  ASAP 2003»
14 years 3 months ago
Automatic Instruction Set Extension and Utilization for Embedded Processors
There is a growing demand for application-specific embedded processors in system-on-a-chip designs. Current tools and design methodologies often require designers to manually spec...
Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giov...
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
14 years 2 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
APCSAC
2005
IEEE
14 years 3 months ago
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
Juan L. Aragón, Alexander V. Veidenbaum