1446 search results - page 160 / 290 » Formal analysis of hardware requirements |
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need ...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract—Embedded system secondary storage size is often constrained, yet storage demands are growing as a result of increasing application complexity and storage of personal dat...
DATE
2007
IEEE
14 years 4 months ago
2007
IEEE
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
ACSAC
2003
IEEE
14 years 3 months ago
2003
IEEE
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
ISSS
2002
IEEE
14 years 3 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...