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ISCAS
2005
IEEE
123views Hardware» more  ISCAS 2005»
14 years 4 months ago
Lower-bound estimation for multi-bitwidth scheduling
In high-level synthesis, accurate lower-bound estimation is helpful to explore the search space efficiently and to evaluate the quality of heuristic algorithms. For the lower-bound...
Junjuan Xu, Jason Cong, Xu Cheng
LCTRTS
2001
Springer
14 years 3 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
14 years 3 months ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
14 years 2 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
ATAL
1995
Springer
14 years 2 months ago
Time, Knowledge, and Choice
Abstract. This article considers the link between theory and practice in agentoriented programming. We begin by rigorously defining a new formal specification language for autono...
Michael Wooldridge