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GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
14 years 29 days ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
DAC
2009
ACM
14 years 8 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
DAC
1998
ACM
14 years 8 months ago
Watermarking Techniques for Intellectual Property Protection
Digital system designs are the product of valuable effort and knowhow. Their embodiments, from software and HDL program down to device-level netlist and mask data, represent caref...
Andrew B. Kahng, John Lach, William H. Mangione-Sm...
ICCAD
2008
IEEE
138views Hardware» more  ICCAD 2008»
14 years 4 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
Amit Agarwal, Jason Cong, Brian Tagiku
ICCAD
2005
IEEE
128views Hardware» more  ICCAD 2005»
14 years 4 months ago
Reducing structural bias in technology mapping
Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we ...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...