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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 6 months ago
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
14 years 6 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
TODAES
2011
107views more  TODAES 2011»
13 years 4 months ago
Scan-based attacks on linear feedback shift register based stream ciphers
—In this paper, we present an attack on stream cipher implementations by determining the scan chain structure of the linear feedback shift registers in their implementations. Alt...
Yu Liu, Kaijie Wu, Ramesh Karri
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
14 years 2 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
Irith Pomeranz, Sudhakar M. Reddy
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
14 years 1 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...