174 search results - page 4 / 35 » Functional Test Generation for Full Scan Circuits |
VLSID
2005
IEEE
14 years 11 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
ICCAD
2000
IEEE
14 years 3 months ago
2000
IEEE
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
VTS
1997
IEEE
14 years 3 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
DAC
1997
ACM
14 years 2 months ago
1997
ACM
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...