138 search results - page 16 / 28 » Functional test generation for delay faults in combinational... |
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
VTS
2003
IEEE
14 years 29 days ago
2003
IEEE
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
DATE
1999
IEEE
14 years 15 hour ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
GLVLSI
1999
IEEE
14 years 6 hour ago
1999
IEEE
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...